1. Technical Field
This Patent Document relates generally to logic level shifting, such as can be used to interface separate circuits/modules operating in different voltage domains (different voltage supply levels).
2. Related Art
Logic level shifters convert logic levels from one voltage domain to another, operating with different supply voltages. The voltage domains can be between different modules of a single IC (integrate circuit), such as core and I/O, or between different ICs.
Logic level shifters can be implemented with single or dual supply configurations. Single supply level shifters enable logic level conversion between voltage domains without requiring separate supply rails (in multi-IC configurations, without requiring separate supply pins). However, a disadvantage of single supply level shifters is increased static power consumption due to increased leakage currents. In particular, as supply voltages are decreased with scaling, the leakage component of total power dissipation increases in significance.
FIG. 1 illustrates a single supply level shifter 10. An input inverter M1/M2 is coupled to a supply network M3/M4 at an INT Node. The input inverter M1/M2 receives a logic signal IN (IN=1,0) and outputs a level shifted OUT (inverted IN) at an OUT Node. A following OUT_X inverter M5/M6 outputs OUT_X (inverted OUT) at an OUT_X Node. The single supply network includes a pull-up PFET M3 in parallel with a diode connected NFET M4. PFET M3 is controlled by feedback control corresponding to OUT_X.
For IN=0 (OUT=1), M2 pulls up the OUT node (M1 is switched off), switching M5 off and M6 on pulling down the OUT_X node. OUT_X=0 is fed back to switch off PFET M3. Initially, the OUT node is pulled up toward VDD (minus the M4 diode drop) by M2/M4. In response to OUT_X=0, PFET M3 switches on to pull up the INT node to VDD (minus a VTH), completing pull-up of the OUT Node to OUT=1 (note that the OUT Node is loaded by M6 pulling down the OUT_X Node).
For IN=1 (OUT=0), M2 is switched off and M1 is switched on, pulling down the OUT node, and switching M6 off and M5 on. M5 pulls up the OUT_X node, and OUT_X=1 switches off PFET M3. With M3 off, the INT node (VS of M2) is below VDD by the M4 diode drop, ensuring M2 is switched off by IN=1.
This type of design for a single supply level shifter presents a number of disadvantages to minimizing leakage, particularly where optimizing logic level rise times is a design consideration. For example, the diode-connected NFET is slow, always on, and loads the INT node (requiring larger M2 and therefore larger M1). The pull-down NFET M6 loads the OUT node, degrading rise time for OUT=1−increasing NFET W can improve OUT_X pull-down, and thus OUT pull-up via M3, but results in higher loading at OUT, which at least partially counters the effect of increasing NFET W.